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Home > Produkte > TX-Standard > TX27 ARM9 > Getting Started > TX-Guide > Pin Assignments 

2 Connector Pin Assignments and Signal Descriptions

Signal names beginning with a “#” symbol indicates that the active, or asserted state, occurs when the signal is at a low voltage level. When “#” is not present, the signal is asserted when at a high voltage level. Differential pairs are indicated by trailing 'P' and 'N' for the positive or negative signal. The following terminology is used to describe columns for the tables located below.

 

TermDescription
IInput
OOutput
I/O

Bi-directional Input/Output Pin

VDDIOI/O type depends on the VDDIO voltage of the module
3V3I/O type: CMOS 3.3V
5VI/O type: CMOS 3.3V to 5V
powerPower supply pin
USB In compliance with the Universal Serial Bus Specification 2.0.
ETNEthernet Media Dependent Interface differential pair signals.
In compliance with IEEE 802.3ab 100Base-T Ethernet Specification.
NCNot Connected
PUPull-up resistor

2.1 Power Supply

PinSignalDescriptiontypeI/O
1-4VDDINModule power supply input (observe DIMM socket contact current rating)powerI
5-7VDDIO

1.8V or 3.3V I/O power supply output

This output can be used for the module side supply of level shifters or of peripherals which are operated at the VDDIO voltage level.

powerO
ModuleRemark
TX27VDDIO=1.8Vmax. 900mA
TX51max. 200mA
TXSD
TX28SVDDIO=3.3Vmax. 20mA
TX25, TX28max. 200mA
TX48, TX53max. 900mA
TX6max. 300mA
9-12VDD33+3.3V Power supply outputpowerO
ModuleRemark
TX27max. 1A
TX51
TXSDmax. 200mA
TX25, TX28, TX48, TX53, TX6VDDIO and VDD33 are connected on the module. Refer to ratings above.

18,26,32,39,50,58,71,82,

88,94,102,111,116,129,

142,147,160,171,200

GND
TX modules operates on a single supply and provide regulated power supply outputs to the baseboard.
The use of level shifters on the baseboard to interface to 3.3V logic allows for universal module selection, because the voltage is automatically translated between VDDIO (1.8V or 3.3V) and VDD33 (3.3V) levels. Level shifters can be omitted on 3.3V only modules like the TX25, but in that case it's not possible to use 1.8V modules anymore.

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2.2 Reset & Bootmode

PinSignalDescriptiontypeI/O
8BOOTMODE

System Boot Mode Select - The operational system boot mode of the module upon system reset is determined by the settings of this pin.

BOOTMODE=H : Boot from NAND / L: Boot from UART/USB

Leave open or connect to VDDIO if not used.

VDDIO

PU

I
ModuleRemark
TX28

Depending on BOOTMODE external pull-up/-down resistors are selected

on LCD interface signals LD0..LD5 and LCD_RS (pin 146). Refer to the

TX28 datasheet for resistor values and level needed at startup!

15#RESET_OUT

Reset Out - Reset carrier board peripherals

#RESET_OUT may be used to reset periphals on the carrier board. Depending on the module type this signal might be asserted automatically by a system reset,but can be controller by a GPIO function during runtime on all modules.

VDDIOO
16#POR

Power On Reset - active low input signal.

Typically a push button reset, pull low to force a reset.

A supervisor circuit is used on the TX module to monitor the power supply. This device assert a processor system reset (POR_B) if the power supply falls outside the programmed threshold or a manual reset (#POR) is asserted externally.

Connect to VIN or leave open if not used.

5V

PU

I
ModuleRemark
TX28

The i.MX28 power-on reset is generated internally.

If low the module power supply is disconnected.

TX28SNot connected
17#RESET_IN

Master Reset - external active low Schmitt trigger input signal. When this signal goes

active, all modules (except the reset module, SDRAMC module, and the clock control module) are reset.

The behaviour might depend on the processor, please refer to the processor reference manual for details.

#RESET_IN is directly connected to theprocessors RESET_B pin.

Pull or connect to VDDIO if not used.

VDDIOI

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2.3 RTC & Power-Button

PinSignalDescriptiontypeI/O
13VBACKUP

DS1339 RTC backup power supply. Supply voltage must be held between 1.3V and  3.7V for proper RTC operation.

This pin can be connected to a primary cell such as a lithium button cell. Additionally, this pin can be connected to a rechargeable cell or a super cap when used with the trickle charge feature.

Refer to DS1339 datasheet for details.

power

I
ModuleRemark
TX25

Connected to BAT_VDD

DRYICE backup power supply input, max. 1.55V

The i.MX25 internal RTC is not supported

TX6 without

DS1339

i.MX6 RTC backup power supply. Supply voltage must be held between 2.9V and 3.3V for proper RTC operation.
14PMIC_PWR_ON

PMIC dependent Function. Leave unconnected if not used.

I

ModuleRemark
TX25No PMIC onboard - Not connected
TX28PSWITCH - Used for chip power on or recovery. PSWITCH is at MID level by default. Refer to i.MX28 refernce manual for details.
TX27, TX51This is an active high push button input which can be used to signal PWR_ON and PWR_OFF events to the CPU by controlling the PMIC EXT_WAKEUP. Refer to LP3972 datashett, page 49 for details.
TX48, TX53

Connected to LTC3589 WAKE. To power down, drive this pin LOW. Refer to LTC3589 datasheet, page 29 for details.

TX6

Connected to PMIC ON.

Refer to PMIC datasheet for details.


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2.4 Ethernet Signals

PinSignalDescriptiontypeI/O

19

21

ETN_TXN

ETN_TXP

100Base-TX or 10Base-T differential transmit output to magnetics.ETNO
20#ETN_LINKLED

Active low LINK ON indication: Active indicates that the link is on.

3V3O
ModuleRemark
TX28, TX48, TX53, TX6Output is driven active when the operating speed is 100Mbps. This LED will go inactive when the operating speed is 10Mbps or during line isolation.
22ETN_3V3+3.3V analogue power supply output to magnetics. This power supply can be turned off on the module to reduce the power consumption in the case Ethernet is not neededpower

O

23

25

ETN_RXN

ETN_RXP

100Base-TX or 10Base-T differential receive input from magnetics.ETNI
24#ETN_ACTLED

Active low ACTIVITY indication: Active indicates that there is Carrier sense (CRS) from the active PMD.

3V3O
ModuleRemark
TX28, TX48, TX53, TX6Output is driven active whenever the device detects a valid link, and blinks indicating activity.
Abbildung 2.1: Ethernet Sample Diagram

2.4.1 Ethernet Physical Layer Layout Guidelines

TX modules are designed for 10 or 100 Mbps Ethernet systems. They are based on IEEE 10BASE-T and 100BASE-TX standards. The IEEE 802.3-2005 standard for 100BASE-TX defines net­working over two pairs of Category 5 unshielded twisted pair cable or Type 1 shielded twisted pair cable. The following recommendations for the printed circuit board layout are not the only way to layout TX modules. Every board designer will have a preference. Complexity, board space, number and types of devices will dictate routing and placement strategies.

2.4.2 Power and Ground Planes

The sections below describe typical 2 and 4 layer board stackups. The goal of the 4 layer designs is to keep the signal routing on outer layers, isolated by the power and ground planes. These power and ground planes also serve the purpose of reference planes for the signal traces. The signal traces should run over continuous reference planes when possible. When 2 layer board designs are required, it remains necessary that the signal traces run over continuous reference planes when possible.

2.4.3 4 Layer Stackup

  • TOP (Layer 1) – Signal with ground plane except where noted.

  • Layer 2 – Continuous ground plane. No signals should be routed on this layer.

  • Layer 3 – Power planes with ground planes except where noted. Signals may be routed on this layer if needed.

  • Bottom (Layer 4) – Signal with ground plane except where noted.

  • Decouple ground floods and ground layer as practical. When signal traces are re-referenced to power island planes, decoupling capacitors (10nF ceramic) are required between the ground plane and power plane.

  • Signal traces routed on bottom layer over power islands that are on Layer 3 layer should have decoupling capacitors (10nF ceramic) near the trace to enable short (direct) return current paths.

  • When signal traces are re-referenced to power island planes, decoupling capacitors (10nF ceramic) are required between the ground plane and power plane as shown below.

 

2.4.4 2 Layer Stackup

  • TOP (Layer 1) – Signal with ground plane except where noted.

  • Bottom (Layer 1) – Ground plane and power islands. A limited number of slow speed signals may be routed on the bottom layer.

  • Signal traces should be surrounded by ground or ground trace along at least one edge. If ground trace is used, it should be connected to ground plane on this layer and decoupled to ground plane on top layer.

Decouple ground planes as practical , as shown below. This will allow short (direct) return current paths when signal traces are re-referenced to different power island planes.

2.4.5 Component Placement

Component placement can affect signal quality, emissions, and component operating temperature. Careful component placement can decrease potential EMI problems and simplify the task of routing traces.

  • If the magnetic is a discrete component, then the distance between the magnetic and the RJ-45 needs to have the highest consideration and be kept to under 25mm (approx. 1 inch) of separation.

  • The distance between the SO-DIMM socket and the magnetics needs to be 20mm or greater. Among PHY vendors, the 25mm (approx. 1 inch) rule is considered good design practice for EMI considerations. The intention is to isolate the PHY from the magnetics.

2.4.6 Design Techniques for EMI Suppression

The following techniques may improve EMI margin.

  • Common mode capacitors may be added to the TX+/- and RX+/- signals for high frequency attenuation , as shown below. One end of each capacitor should be connected to the system ground plane, and placed within 10mm (approx. 400mils) of the magnetics. Typical capacitance values should be between 10pF and 22pF. Values higher than 22pF may negatively impact the TX and RX signalling.

 
  • Common mode chokes may be added to the TX and RX differential pairs as shown below. The common mode chokes should be placed within 10mm (approx. 400mils) of the integrated RJ45 module, and on the magnetics side of the common mode EMI suppression capacitors. Typical common mode impedance of the common mode choke selected should be 2kΩ@100MHz or higher.
  • In general, no ground plane should extend under the TX and RX differential pairs, under the magnetics, or under the RJ45 jack. In the case where common mode capacitors used for EMI suppression, a ground plane may be located under the TX and RX signals, however the plane must not exceed beyond the capacitors. When designing 4 layer boards, the ground plane should exist on layer 4, assuming the differential pair is routed on layer 1. On 2 layer boards, the ground plane can be located on layer 2, the adjacent layer to the TX and RX signal pairs. Under no circumstances should a ground plane exist under the magnetics, the RJ45 connector or in between the magnetics and RJ45 connector.

2.4.7 Controlled Impedance for Differential Signals

 

 

The 802.3-2005 specifications requires the TX and RX lines to run in differential mode. The TXP and TXN are a differential pair and need to be designed to a 100 ohm differential impedance. The RXP and RXN traces are also a differential pars and need to be designed to a 100 ohm differential impedance target.

The board designer must maintain 100 ohm differential impedance in the layout for all differential pairs. For differential dielectric thickness, copper weight or board stack-up, trace width and spacings will need to be calculated.

Differential pair nets must maintain symmetry. TXP and TXN must be equal length and symmetric with regards of shape, length, and via count. RXP and RXN must also be equal length and symmetric.

Isolation of TX/RX traces. The TX/RX traces must be isolated from nearby circuitry and signals. Maintain a distance of parts to lines that are greater than or equal to 5 times the distance of the spacing between the traces. Do not route differential pairs under parts. Do not cross TX/RX lines with other PCB traces unless the traces are on the opposite side of the ground plane from TX/RX.

2.4.8 Magnetics Module

The magnetics module has a critical effect on overall IEEE and emissions conformance. The device should meet the performance required for a design with reasonable margin to allow manufacturing variation. Occasionally, components that meet basic specifications may cause the system to fail IEEE testing, because of interactions with other components or the Printed Circuit Board itself. Carefully qualifying new magnetics modules can go a long way toward preventing this type of problem.

Suggested magnetics have not been tested in order to verify proper operation. This category of magnetic has been evaluated by the contents of the vendor supplied data sheet and legacy performance only. However, the designer can assume with some degree of confidence, that with proper PCB design techniques, the magnetics presented as suggested magnetics will perform to high standards.

Qualified magnetics have been tested by the PHY vendor in order to verify proper operation. The designer can assume with a high degree of confidence, that with proper PCB design techniques, the qualified magnetics perform to the highest standards.


VendorPart NumberPackageTempStatus
PulseH110216-pin SOIC0°..+70°C Qualified
HaloTG110-RP55N516-pin SOIC0°..+70°C Qualified
HaloHFJ11-RP26E-L12RLIntegrated RJ450°..+70°C Qualified
DeltaRJSE1R5310AIntegrated RJ45 0°..+70°CQualified
PulseJ0011D01BIntegrated RJ450°..+70°CSuggested
BothhandTS6121C16-pin SOIC0°..+70°CSuggested
BothhandLU1S041X-43Integrated RJ450°..+70°CSuggested
PulseHX110216-pin SOIC-40°..+85°CQualified
HaloTG110-RPE5N516-pin SOIC-40°..+85°CQualified
HaloHFJ11-RPE26E-L12RLIntegrated RJ45-40°..+85°CQualified
TDKTLA-6T717WIntegrated RJ45-40°..+85°CQualified
DeltaLFE8505T16-pin SOIC-40°..+85°CQualified
Midcom000-7090-37R16-pin SOIC-40°..+85°CSuggested
MidcomMIC66211-5171T-LF3Integrated RJ45-40°..+85°C Suggested
Elec & Eltek820-M0323R16-pin SOIC -40°..+85°CSuggested

Midcom /

Würth-Elektronik

MIC24013-5101T-LF3

749 901 121 11

Integrated RJ45 0°..+70°CUsed on Starterkit 5
Bel StewartSI-60005-FIntegrated RJ45N/A

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2.5 USB

PinSignalDescriptiontypeI/O

27

34

USBH_VBUSEN

USBOTH_VBUSEN

This pin is used to enable the external VBUS power supply.3V3O

28

26

#USBH_OC

#USBOTH_OC

Active low over-current indicator input connected to a GPIO.

This signal can be used as an input only.

3V3I

30

38

USBH_VBUS

USBOTG_VBUS

VBUS pin of the USB cable. This pin is used for the VBUS comparator inputs.

5V

I
ModuleRemark
TX25USBH_VBUS / USBOTG_VBUS unused / Not connected
TX28USBH_VBUS unused / Not connected

31

29

USBH_DP

USBH_DM

USB Host port differential data signalUSBI/O

37

35

USBOTG_DP

USBOTG_DM

USB OTG port differential data signalUSBI/O
33USBOTG_IDID pin of the USB cable. For an A-Device ID is grounded. For a B-Device ID is floated.5VI
ModuleRemark
TX25/TX28/TX48/TX53/TX6USBOTG_VBUSEN, USBOTG_OC are also used for the 2nd CAN interface. In that case the VBUSEN/OC functionality may be omitted or other GPIO's may be used instead.

2.5.1 USB Physical Layer Layout Guidelines

The TX modules includes the physical layer interface (PHY) for systems using Hi-Speed USB. Proper design techniques must be used in printed circuit board (PCB) layout to maintain the signal integrity required for 480 Mbps operation.

2.5.2 Controlled Impedance for USB Traces

The USB 2.0 specification requires that the USB DP/DM traces maintain a nominal 90 Ohms +/- 15% differential impedance (see USB specification Rev. 2.0, paragraph 7.1.1.3 for more details). In the example design the traces are 7 mil (175um) wide with line spacing of 7 mils. These numbers are derived for 5 mil (125um) distance from ground reference plane. A continuous ground plane is required directly beneath the DP/DM traces and extending at least 5 times the spacing width to either side of DP/DM lines.

Maintain symmetry between DP/DM lines in regards to shape and length.

Single sided impedance is not as critical as differential impedance. A range of 42 to 78 Ohms is acceptable (equivalently, common mode impedance must be between 21 Ohms and 39 Ohms).

The figures show DP/DM traces with approximately equal trace length and symmetry. It is important to maintain a conductor width and spacing that provides differential and common mode impedance compliant with the USB specification. Use 45 degree turns to minimize impedance discontinuities.

 

2.5.3 Isolation of DP/DM Traces

The DP/DM lines must be isolated from nearby circuits and signals. Maintain a distance of components to lines that is greater or equal to 5 times the distance of the spacing between the traces. Do not route differential pairs under components. Do not cross DP/DM lines with other PCB traces unless the traces are on the opposite side of the ground plane from DP/DM. Route DP/DM over solid ground plane with no ground plane splits under the traces.

2.5.4 Isolated shielding on the USB connector

 

The figure shows the Mini-AB connector housing is isolated but AC coupled to the device ground. Industry convention is to ground only the host side of the cable shield. This is done to provide cable shielding while preventing possible ground currents from flowing in the USB cable if there happens to be a potential difference between the host and device grounds. If DC grounding is required replace C12 with a zero Ohms resistor.

In OTG applications the shield may be DC grounded at both ends of the cable.

2.5.6 USB recommendations1

In summary use the following recommendations for the USB.

  • Route DP and DM signals on the top or bottom layer of the board
  • The trance width and spacing of the DP and DM signals should be such that the differential impedance is 90 Ω.
  • Route traces over continuous planes (power and ground)

    • They should not pass over any power/GND plane slots or anti-etch.
    • When placing connectors, make sure the ground plane clearouts around each pin have ground continuity between all pins.

  • Maintain the parallelism (skew matched) between DP and DM; these traces should be the same overall length.
  • Do not route DP and DM traces under oscillators or parallel to clock traces and/or data buses.
  • Minimize the lengths of high speed signals that run parallel to the DP and DM pair.
  • Keep DP and DM traces as short as possible.
  • Route DP and DM signals with a minimum amount of corners. Use 45-degree turns instead of 90- degree turns.
  • Avoid layer changes (vias) on Dm and Dp signals. Do not create stubs or branches.

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2.6 I2C

PinSignalDescriptiontypeI/O
40I2C_DATAI2C DataVDDIOI/O
41I2C_CLKI2C ClockVDDIOO
ModuleDevices connected to this I2C bus

TX25, TX27, TX28S,

TX51, TX53, TX6

No devices are connected to this I2C bus.

No pullup's are used on the module

NameTypeSpeed [kbps]Address
TX28DS1339RTC4001101000 r/w
PCA9554IO4000100000 r/w
TX48DS1339RTC4001101000 r/w
LTC3589PMIC4000110100 r/w

 

The I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices. The flexible I2C allows additional devices to be connected to the bus for expansion and system development.

2.6.1 Example I2C Voltage Level Translator (TX27 and TX51 only)

 

The Texas Instruments PCA9306 allows bidirectional voltage translations between 1.2 V and 5 V, without the use of a direction pin.

Be aware of the PCA9306 min. supply voltage: VREF2 > VREF1 + 0.6V. Because of this limitation a Texas Instruments TXS0102 should be used instead if the design is intended to be used with 1.8V and 3.3V TX modules.

As with the standard I2C system, pullup resistors are required to provide the logic high levels on the translator's bus. The PCA9306 has a standard open-collector configuration of the I2C bus. The size of these pullup resistors depends on the system, but each side of the repeater must have a pullup resistor. The device is designed to work with standard-mode and fast-mode I2C devices, in addition to SMBus devices. Standard-mode I2C devices only specify 3 mA in a generic I2C system where standard-mode devices and multiple masters are possible. Under certain conditions, high termination currents can be used.

2.6.2 I2C recommendations2

 

RecommendationExplanation
Verify the target I2C interface clock rates.The bus can only operate as fast as the slowest peripheral on the bus. If faster operation is required, move the slow devices to another I2C port. A slow peripheral may unpredictably take over the bus or might malfunction in some other way.
Verify that the target I2C address range is supported and does no conflict with other peripherals. If there is an unavoidable address conflict, move the offending device to another I2C port.If it is undesirable to move a conflicting device to another I2C port, review the peripheral operation to see if it supports remapping the address.
Do not place more than one set of pullup resistors on the I2C linesThis can result in excessive loading. Good design practice is to place one pair of pullups only.

 

 

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2.7 PWM / 1-WIRE

PinSignalDescriptiontypeI/O
42PWM

Pulse-Width Modulator (PWM) Output

VDDIOO
ModuleRemark
TX51Be aware of the voltage level on this pin: 3.1V instead of 1.8V
43OWIRE

1-Wire

VDDIOI/O
ModuleRemark
TX28/TX48/TX6No 1-Wire controller - a GPIO is used instead
1-Wire is a registered trademark of Dallas Semiconductor for a device communications bus systems designed by Dallas Semiconductor that provides low-speed data, signalling and power over a single signal, albeit using two wires, one for ground, one for power and data. 1-Wire is similar in concept to I2C, but with lower data rates and longer range. It is typically used to communicate with small inexpensive devices.

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PinSignalDescriptiontypeI/O
44CSPI_SS0Slave Select bidirectional, selectable polarity signal, output in master mode, and input in slave mode.VDDIOI/O
45CSPI_SS1VDDIOI/O
46CSPI_MOSIMaster Out Slave In bidirectional signal, which is TxD output signal from the data shift register in master mode. In Slave mode it is RxD input to the data shift register.VDDIOI/O
47CSPI_MISOMaster In Slave Out bidirectional signal, which is RxD input signal to the data shift register in master mode. In Slave mode it is TxD output from the data shift register.VDDIOI/O
48CSPI_SCLKCSPI Clock bidirectional signal, which is CSPI clock output in master mode. In slave mode it is an input CSPI clock signal.VDDIOI/O
49CSPI_RDYSerial Data Ready signal - This input signal is used for hardware control only in master mode. It indicates that external SPI slave is ready to receive data. It will edge or level trigger a CSPI burst if used. If the hardware control enabled, CSPI will transfer data only when external SPI slave is ready.VDDIOI/O

 

The i.MX processors contains Configurable Serial Peripheral Interface (CSPI) modules that allow rapid data communication with fewer software interrupts than conventional serial communications. Each CSPI is equipped with two data FIFOs and is a master/slave configurable serial peripheral interface module, allowing processor to interface with both external SPI master and slave devices.

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2.9 SDIO Interfaces

PinSignalDescriptiontypeI/O

51,

95

SD1_CD

SD2_CD

SD Card Detect - connected to a GPIOVDDIOI

52,

96

SD1_D[0]

SD2_D[0]


SD Data bidirectional signals


VDDIOI/O

53,

97

SD1_D[1]

SD2_D[1]

54,

98

SD1_D[2]

SD2_D[2]

55,

99

SD1_D[3]

SD2_D[3]

56,

100

SD1_CMD

SD2_CMD

SD Command bidirectional signalVDDIOI/O

57,

101

SD1_CLK

SD2_CLK

SD Output Clock.VDDIOO
ModuleRemark
TX25, TX28, TX48Only one SD-Card available on standard pinout, SD Interface 2 is not used / not connected
TX28Pin 101 is used as ENET_CLK

 

The TX pinout provides two dedicated SDIO interfaces. SDIO stands for Secure Digital Input Output which can also be used for SD-Memory-Cards.

2.9.1 SD-Card example diagram using level shifters

 

No external pullups are needed here. Each port of the TXS0108E has an internal pull-up resistor. These have a value of 40 kΩ when the output is driving low and a value of 4 k Ω when the output is driving high. Unfortunately the card detect feature commonly used for Micro-SD cards on DAT3/CD cannot be used. A dedicated card detect switch is required.

 

2.9.2 SD-Card example diagram only for 3.3V modules

 

Either the use of the processor internal pullups or the use of pullups on the baseboard is possible.

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2.10 UARTs

PinSignalDescriptiontypeI/O

59,

63,

67

UART1_TXD

UART2_TXD

UART3_TXD

Transmit Data output signalVDDIOO

60,

64,

68

UART1_RXD

UART2_RXD

UART3_RXD

Receive Data input signalVDDIOI

61,

65,

69

UART1_RTS

UART2_RTS

UART3_RTS

Request to Send input signalVDDIOI

62,

66,

70

UART1_CTS

UART2_CTS

UART3_CTS

Clear to Send output signalVDDIOO

2.10.1 UART Example diagram

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2.11 Keypad Interface

PinSignalDescriptiontypeI/O
72KP_COL[0]Keypad Column selection signals.VDDIO
73KP_COL[1]VDDIO
74KP_COL[2]VDDIO
75KP_COL[3]VDDIO
76KP_COL[4]VDDIO
77KP_ROW[0]Keypad Row selection signals.VDDIO
78KP_ROW[1]VDDIO
79KP_ROW[2]VDDIO
80KP_ROW[3]VDDIO
81KP_ROW[4]VDDIO
ModuleRemark
TX28A PCA9554 8-bit I2C-bus I/O port is used for KP_COL[0-3] and KP_ROW[0-3] KP_COL[4], KP_ROW[4] is not part of the keypad interface, used for CAN instead.
TX25, TX48, TX53, TX6KP_COL[4], KP_ROW[4] can also be used for the 1st Can interface.

 

The Keypad Port (KPP) is designed to interface with the keypad matrix with 2-point contact or 3-point contact keys. The KPP is designed to simplify the software task of scanning a keypad matrix. With appropriate software support, the KPP is capable of detecting, debouncing, and decoding one or multiple keys pressed simultaneously on the keypad.

 

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2.12 Digital Audio Ports

PinSignalDescriptiontypeI/O

83

89

SSI1_INT

SSI2_INT

Interrupt

84

90

SSI1_RXD

SSI2_RXD

Receive serial data

85

91

SSI1_TXD

SSI2_TXD

Transmit serial data

86

92

SSI1_CLK

SSI2_CLK

Serial clock

87

93

SSI1_FS

SSI2_FS

Frame Sync
ModuleRemark
TX28S, TX48Only one SSI port available, SSI2 pins are not connected
TX28, TX28SOn this module the SSI is a half-duplex serial port

 

The SSI is a full-duplex, serial port that allows the chip to communicate with a variety of serial devices. These serial devices can be standard CODer-DECoder (CODECs), Digital Signal Processors (DSPs), microprocessors, peripherals, and popular industry audio CODECs that implement the inter-IC sound bus standard (I2S) standard.

SSI is typically used to transfer samples in a periodic manner. The SSI consists of independent transmitter and receiver sections with independent clock generation and frame synchronization.

 

Audio Codec example:

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2.13 CMOS Sensor Interface

PinSignalDescriptiontypeI/O
103-110CSI1_DSensor port data (8 bit)VDDIOI
112CSI1_HSYNCSensor port horizontal syncVDDIOI
113CSI1_VSYNCSensor port vertical syncVDDIOI
114CSI1_PIXCLKSensor port data latch clockVDDIOI
115CSI1_MCLKSensor port master clockVDDIOO
ModuleRemark
TX28The TX28 has no camera interface. Refer to TX28 data sheet for alternate usage.

 

The CMOS Sensor Interface (CSI) enables the chip to connect directly to external CMOS image sensors. CMOS image sensors are separated into two classes, dumb and smart. Dumb sensors are those that support only traditional sensor timing (Vertical SYNC and Horizontal SYNC) and output only Bayer and statistics data, while smart sensors support CCIR656 video decoder formats and perform additional processing of the image (for example, image compression, image pre-filtering, and various data output formats).

The standard CSI can support to connect one 8-bit sensor.

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2.14 Extended and 2nd CMOS Sensor Interface (TX51, TX53 and TX6 only)

PinSignalDescriptiontypeI/O
161-164CSI1_D[8-11]Sensor port data (4 bit)VDDIOI
152-159CSI2_D[12-19]2nd Sensor port dataVDDIOI
151CSI_HSYNC2nd Sensor port horizontal syncVDDIOI
150CSI2_VSYNC2nd Sensor port vertical syncVDDIOI
149CSI2_PIXCLK2nd Sensor port data latch clockVDDIOI
148CSI2_MCLK2nd Sensor port master clockVDDIOO
ModuleRemark
TX25, TX27, TX28, TX48Not available - other module specific functions are used on these pins.

 

TX51 and TX53 provide a second camera interface and four additional data bits for the first camera interface. The complete interface is available on the module specific section of the TX-Standard pinout.

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2.15 LCD Interface

PinSignalDescriptiontypeI/O

117-128,

130-141

LCD_D[0-23]LCD Data
143HSYNCLine Pulse or HSync
144VSYNC

Frame Sync or VSync-This signal also serves as the

clock signale output for gate; driver (dedicated signal SPS

for Sharp panel HR-TFT)

145OE_ACDAlternate Crystal Direction/Output Enable
146LSCLKShift Clock

The LCD Controller of the i.MX processors provides display data for external greyscale or color LCD panels. The LCD Controller is capable of supporting black-and-white, greyscale, passive-matrix color (passive color or CSTN), and active-matrix color (active color or TFT) LCD panels.

The TX LCD Interface defines a generic 24 bit Panel Interface LCD_D[23..0]. The TFT color channel assignments are shown in the table below:

LCD_D23222120191817161514131211109876543210

TX28

TX51

TX53

TX6

LD

23

LD

22

LD

21

LD

20

LD

19

LD

18

LD

17

LD

16

LD

15

LD

14

LD

13

LD

12

LD

11

LD

10

LD

9

LD

8

LD

7

LD

6

LD

5

LD

4

LD

3

LD

2

LD

1

LD

0

TX48

LD

4

LD

3

LD

2

LD

1

LD

0

LD

16

LD

18

LD

21

LD

10

LD

9

LD

8

LD

7

LD

6

LD

5

LD

19

LD

22

LD

15

LD

14

LD

13

LD

12

LD

11

LD

17

LD

20

LD

23

TX25

TX27

LD

17

LD

16

LD

15

LD

14

LD

13

LD

12

GP

IO

GP

IO

LD

11

LD

10

LD

9

LD

8

LD

7

LD

6

GP
IO

GP

IO

LD

5

LD

4

LD

3

LD

2

LD

1

LD

0

 

GP

IO

 

GP

IO

24bpp

 

18bpp

R7

 

R5

R6

 

R4

R5

 

R3

R4

 

R2

R3

 

R1

R2

 

R0

R1

 

 

R0

 

 

G7

 

G5

G6

 

G4

G5

 

G3

G4

 

G2

G3

 

G1

G2

 

G0

G1

 

 

G0

 

 

B7

 

B5

B6

 

B4

B5

 

B3

B4

 

B2

B3

 

B1

B2

 

B0

B1

 

 

B0

 

 

16bpp

R4

R3R2R1R0G5G4G3G2G1G0B4B3B2B1B0
12bppR3R2R1R0G3G2G1G0B3B2B1B0
With this assignment the two module types – 18bpp like the TX25 and TX27 and 24bpp like the TX51 – can be used on the same carrier board without any change. On 18bpp modules the unused bits are always connected to General Purpose IOs to be able to drive these to a defined level.
ModuleRemark3
TX48The blue and red color assignments to the LCD data pins are reversed when operating in RGB888 (24bpp) mode compared to RGB565 (16bpp) mode. Using the LCD Controller with this connection scheme limits the use of RGB565 mode. Any data generated for the RGB565 mode requires the red and blue color data values be swapped in order to display the correct color.

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2.16 LVDS/SATA option (TX53, TX6 only)

As an ordering option the TX53 and TX6 are available with a dual LVDS and SATA interface instead of the parallel LCD interface.

In that case the LCD interface signals LD0..LD19 are used to bring out the processors LVDS interfaces. In addition to this the SATA interface is available on pins LD20..LD

2.16.1 LVDS pin mapping

 

LVDS interface 0

 

LCD_D1918171615141312119
Pin137136135134133132131130128126
SignalTX0_NTX1_NTX0_PTX1_PTX2_NCLK_NTX2_PCLK_PTX3_NTX3_P

 

LVDS interface 1

 

LCD_D10876543210
Pin127125124123122121120119118117
SignalCLK_PCLK_NTX0_PTX3_PTX0_NTX3_NTX1_PTX2_PTX1_NTX2_N

2.16.2 LVDS recommendations4

Use the following recommendations for the LVDS.

  • Follow standard high-speed differential routing rules for signal integrity.
  • Each differential pair should be length matched to +/- 5 mils.
  • LVDS differential pairs should have a differential impedance of 100 Ω.

2.16.3 SATA pin mapping

 

LCD_D23222120
Pin141140139138
SignalSATA_TXPSATA_RXPSATA_TXMSATA_RXM

2.16.4 SATA recommendations5

Use the following recommendations for the SATA.

  • SATA differential paris should have a differential impedance of 100 Ω.
  • Each differential pair should be length matched to +/- 5 mils.
  • Follow standard high-speed differential routing rules for signal integrity.

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2.17 CAN Interface

PinSignalDescriptiontypeI/O
76CAN1-TXThis is the transmit signal to the CAN bus transceiver.VDDIOO
81CAN1-RXThis is the receive signal from the CAN bus transceiver.VDDIOI
34CAN2-TXThis is the transmit signal to the CAN bus transceiver.VDDIOO
36CAN2-RXThis is the receive signal from the CAN bus transceiver.VDDIOI
ModuleRemark
TX27, TX51Not available - default functions are used on these pins.

Some TX modules provides a FlexCAN communication controller that implements the CAN protocol according to the CAN 2.0B protocol specification. The CAN protocol was designed primarily (but not solely) to meet requirements suitable for a serial data bus in vehicle applications, including: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness, and sufficient bandwidth. A CAN Transceiver is needed on the baseboard to connect the system to the CAN bus. The Texas Instruments SN65HVD23x operates with a single 3.3V supply and can be connected directly to the 3.3V TX modules:

 

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2.18 2nd Ethernet RMII (TX28 only)

PinSignalDescription
15RESET_BEthernet PHY reset. This signal is also connected to the TX28 onboard Ethernet PHY.
101ENET_CLKEthernet PHY clock. This signal is also connected to the TX28 onboard PHY. This clock signal is split at the driver side on the TX28. The trace length on the baseboard should be about 35mm.
152ENET1_RXD0Bit 0 of the 2 data bits that are sent by the transceiver on the receive path.
153ENET1_RXD1Bit 1 of the 2 data bits that are sent by the transceiver on the receive path.
154ENET1_TXD0Bit 0 of the MAC transmit data to the transceiver
155ENET1_TXD1Bit 1 of the MAC transmit data to the transceiver
156ENET1_TX_ENIndicates that valid transmission data is present on TXD[1:0]
157ENET1_RX_ENReceive Data Valid
197ENET_INTEthernet PHY interrupt. This signal is wired or with the TX28 onboard Ethernet PHY interrupt.
198ENET_MDCENET_MDC
199ENET_MDIOENET_MDIO

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2.19 TV out (TX51, TX53 only)

PinSignalDescriptiontypeI/O
168TVDAC_IOBTriple Video Digital-to-Analog Converter (TVDAC); supports HD720p/1080p, PAL/NTSC or VGA output for direct connection to TV or LCD projectoranalogO
169TVDAC_IOGanalogO
170TVDAC_IORanalog

O

 

Rset = 1.05 kΩ ±1%, resistor on TVDAC_VREF pin to GND

A 75-Ω termination is already done on the module:


2.19.1 TV Encoder Recommendations6

Use the following recommendations for the TV encoder.

  • For the TV/VGA interface, the IOR, IOG, and IOB signals must have 75-Ω imepedance.

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2.20 PCI express (TX6 only)

PinSignalDescriptiontypeI/O

166,

168

CLK1_N

CLK1_P

Alternate reference clock for PCIeLVDSI/O

167,

169

PCIE_RXM

PCIE_RXP

PCI Express receive differential pairLVDSI

170,

172

PCIE_TXM

PCIE_TXP

PCI Express transmit differential pairLVDSO
The TX6 provides a ×1 PCIe lane. The PCIe module supports PCI Express Gen 2.0 interfaces at 5 Gb/s. It is also backwards compatible to Gen 1.1 interfaces at 2.5 Gb/s.

2.20.1 PCI Express interface recommendations7

 

2.20.1.1 PCI Express general routing guidelines

Use the following recommendations for PCI Express general routing:

  • The trace width and spacing of the lanes x1 signals should be such that the differential impedance is 85 Ω +/- 10%.
  • Route traces over continuous planes (power and ground). Avoid split planes, plane slots, or anti-etch.
  • Maintain the parallelism (skew matched) between differential signals; these traces should be the same overall length.
  • Keep signals with traces as short as possible.
  • Route signals with a minimum amount of corners. Use 45-degree turn instead of 90-degree turns.
  • Do not create stubs or branches.
  • Maintain symmetry or differential pair routing.

 

2.20.1.2 PCI Express coupling lane

All signals are directly connected on the TX6 module. Refer to the NXP Hardware Development Guide for a guideline to couple the signals. Consult the PCISig documentation for detailed information.

2.20.2 PCIe recommendations8

 

RecommendationExplanation
Termination is required on the differential clock lines. Connect two 49.9 Ω resistors, one between REFCLK- and GND, the other between REFCLK+ and GND. Alternately, Connect a 100 Ω resistor between REFCLK- and REFCLK+.Termination is required on the differential clock lines. Connect two 49.9 Ω resistors, one between REFCLK- and GND, the other between REFCLK+ and GND. Alternately, Connect a 100 Ω resistor between REFCLK- and REFCLK+.

 

 

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2.21 GPIO and module specific signals

PinSignalDescriptiontypeI/O
148-159GPIO[0-11]General Purpose Input/OutputVDDIOI/O

161-170,

172-182,

184-199

Module specific interfaces - refer to datasheet for details

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1 NXP Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors, Chap. 2.11
2 NXP Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors, Table 1-4
3 AM335x ARM Cortex-A8 Microprocessors (MPUs) Silicon Errata
4 NXP Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors, Chap. 2.10
5 NXP Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors, Chap. 2.9
6 NXP i.MX53 System Development User’s Guide, MX53UG, Chap. 2.7
7 NXP Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors, chap. 2-7
8 NXP Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors, Table 1-10

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